This invention relates generally to the field of telecommunications, and more particularly to a serialized bus communication and control architecture for network element in a telecommunications system.
Telecommunication systems include customer premise equipment (CPE), local loops connecting each customer premise to a central office (CO) or other node, the nodes providing switching and signaling for the system, and internode trunks connecting the various nodes. The customer premise equipment (CPE) includes telephones, modems for communicating data over phone lines, computer and other devices that can directly communicate video, audio, and other data over a data link. The network nodes include traditional circuit-switch nodes which have transmission paths dedicated to specific users for the duration of a call and employ continuous, fixed-bandwidth transmission as well as packet-switch nodes that allow dynamic bandwidths, dependent on the application. The transmission media between the nodes may be wireline, wireless, or a combination of these or other transmission medias.
Telecommunication nodes typically use parallel buses across a backplane between a node controller and service, line, or other units of the node. On a parallel bus, integrity can be effected by the insertion and removal of units on the bus. In addition, a single unit failure can cause the bus to also fail. Another problem with parallel buses is that a large amount of input/output (I/O) pins to the backplane are required for a wide bus. Although multiplexing of the bus can reduce the pin count, a substantial number of pins are nevertheless required.
The present invention provides a serialized bus communication and control architecture for a network element or other suitable node. In particular, the serialized bus includes discrete point-to-point serial channels between a controller and service units to form a star topology communication and control architecture.
In accordance with one embodiment of the present invention, a serial bus communication system for communicating across a backplane of a node includes a control unit having a serial bus controller. A plurality of service units each include a serial bus terminator. A serial bus includes a discrete serial channel for each service unit. The serial channel connects the serial bus terminator to the serial bus controller. The serial bus controller is operable to direct a message for a service unit on the serial bus to only the serial channel of the services unit.
In accordance with another aspect of the present invention, a system for communicating between units across a backplane and a node includes a control unit having an address counter and a plurality of service units each having a local address counter. A bus connects the service units to the control unit. The control unit is operable to transmit a request for a data transfer operation at a service unit to the service unit without a memory address location for the data transfer operation. The service unit is operable to shift a previous address stored in the local address counter to a next address and to perform the data transfer operation at the next address.
In accordance with still another aspect of the present invention, a serial bus communication system for communicating across the back plane of a node includes a control unit including a serial bus controller and a plurality of service units each having a serial bus terminator. A serial bus includes a discrete serial channel for each service unit. The serial channel connects the serial bus terminator to the serial bus controller. The serial bus terminator is operable to transmit to the serial bus controller on an upstream link of its serial channel an unsolicited interrupt signal identifying a received interrupt. The serial bus controller includes a discrete monitor for each service unit. The monitor is connected to the upstream link of each serial channel and operable to receive the interrupt signal and to inform an interrupt processor of the interrupt and the service unit at which the interrupt was received.
In accordance with yet another aspect of the present invention, a system for resetting remote resources for synchronization or in response to error or failures with a controller or other unit includes a control unit and a plurality of service units. A serial bus includes a discrete serial channel for each service unit. The serial channel connects the service unit to the control unit and includes a clock link operable to transmit a clock signal from the control unit to the service unit. The control unit is operable to interrupt the clock signal on the clock linked to a service unit in response to a reset event for the service unit. The service unit includes a clock detector operable to detect an interruption in the serial link clock signal and to reset at least a portion of the service unit""s serial bus terminator in response to the interruption.
Technical advantages of the present invention include providing a serialized bus communication and control architecture for a network element. The serial star architecture of the bus provides isolation between each serial unit and the controller unit. As a result, failure of one or more service units will not effect communication between the controller and remaining service units.
Another technical advantage of the present invention includes providing simultaneous processor access and direct memory access (DMA) over the serial bus. In particular, the processor provides linked buffer descriptor lists to the DMA controller for processing which frees up the processor to execute other messaging or other code processes. While the DMA controller is processing a linked buffer descriptor list and communicating with a service unit, the processor may also directly access another service unit over the serial bus. Accordingly, the controller unit can multitask to improve efficiency of the controller and the node.
Still another technical advantage of the present invention includes providing prioritized processing. In particular, high and low priority link-list processing is provided to allow time critical buffer transfers to interrupt non-critical buffer transfers. In addition, DMA operations to a service unit can be interrupted for direct processor access to that same unit. As a result, high-priority operations need not wait until lower-priority operations have completed.
Yet another technical advantage of the present invention includes providing increased data throughput on a communication link. In particular, portions of the DMA controller are divided between the controller and service units, with address counters being embedded in each service unit. Buffer or block data transfers are performed by sending the first frame with the start address for the transfer operation in the frame, which is then loaded into the address counter in the service unit. Addressing for the consecutive frames is obtained by incrementing the address counters and thus need not be transmitted in the consecutive frames. As a result, overhead is reduced and data throughput is increased for transmissions across a serial link.
Still another technical advantage of the present invention includes reducing pin count on the control and service units in the node. In particular, the serial bus requires only three input/output (I/O) pins on each service unit, which are clock, downstream data, and upstream data. Virtual wires are created on the backplane for six interrupts from each service unit to the control unit and sixteen discrete control signals from the control unit to each service unit. The interrupt virtual wires are implemented by the service unit decoding an interrupt and recreating the appropriate priority interrupt to the processor on the control unit. The control unit controls sixteen discrete logic signal outputs on each service unit by writing to memory map registers via the serial channel. In addition, service units are reset by interruption of the clock signal. As a result, pin count and wiring is greatly reduced in the node.
Other technical advantages of the present invention will be readily apparent to one skilled in the art from the following figures, description, and claims.